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authorChris Dearman <chris@mips.com>2007-09-19 00:46:32 +0100
committerRalf Baechle <ralf@linux-mips.org>2008-04-28 17:14:25 +0100
commit962f480e0f9024ecdcfe2ba1d216c038ee328ced (patch)
tree7bdc4f14bd9e894ed3178b3a9b6ec235710868a6 /arch/mips/mm/tlb-r4k.c
parent0bfa130e741f8f73a7bbf6a89aad4816e9094a71 (diff)
downloadlwn-962f480e0f9024ecdcfe2ba1d216c038ee328ced.tar.gz
lwn-962f480e0f9024ecdcfe2ba1d216c038ee328ced.zip
[MIPS] All MIPS32 processors support64-bit physical addresses.
Still, only the 4K may actually implement it. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/tlb-r4k.c')
-rw-r--r--arch/mips/mm/tlb-r4k.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 63065d6e8063..5ce2fa745626 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -299,7 +299,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
idx = read_c0_index();
ptep = pte_offset_map(pmdp, address);
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
write_c0_entrylo0(ptep->pte_high);
ptep++;
write_c0_entrylo1(ptep->pte_high);