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| author | Ralf Baechle <ralf@linux-mips.org> | 2008-03-08 09:56:28 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-03-12 14:14:41 +0000 |
| commit | 234fcd1484a66158b561b36b421547f0ab85fee9 (patch) | |
| tree | b63fbb134fd673e1713f0462e6e0642b418da616 /arch/mips/mipssim | |
| parent | 1af0eea21431bed5d07dffc0fefab57fd72f7e90 (diff) | |
| download | lwn-234fcd1484a66158b561b36b421547f0ab85fee9.tar.gz lwn-234fcd1484a66158b561b36b421547f0ab85fee9.zip | |
[MIPS] Fix loads of section missmatches
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mipssim')
| -rw-r--r-- | arch/mips/mipssim/sim_time.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c index e39bbe989da3..881ecbc1fa23 100644 --- a/arch/mips/mipssim/sim_time.c +++ b/arch/mips/mipssim/sim_time.c @@ -83,7 +83,7 @@ static void mips_timer_dispatch(void) } -unsigned __init get_c0_compare_int(void) +unsigned __cpuinit get_c0_compare_int(void) { #ifdef MSC01E_INT_BASE if (cpu_has_veic) { |