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| author | Julia Lawall <Julia.Lawall@inria.fr> | 2022-04-30 21:03:10 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2022-05-04 22:22:59 +0200 |
| commit | 94bd83e45acdd72b81545ff25324a13bc5cae54e (patch) | |
| tree | 3f5d2f5e98d180d44794feb43cb3f1d9418b8200 /arch/mips/kernel | |
| parent | 7671f9674b474505de289b548206ef48b0f5ceac (diff) | |
| download | lwn-94bd83e45acdd72b81545ff25324a13bc5cae54e.tar.gz lwn-94bd83e45acdd72b81545ff25324a13bc5cae54e.zip | |
MIPS: fix typos in comments
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/cmpxchg.c | 2 | ||||
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 2 | ||||
| -rw-r--r-- | arch/mips/kernel/idle.c | 2 | ||||
| -rw-r--r-- | arch/mips/kernel/perf_event_mipsxx.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/kernel/cmpxchg.c b/arch/mips/kernel/cmpxchg.c index ac9c8cfb2ba9..e974a4954df8 100644 --- a/arch/mips/kernel/cmpxchg.c +++ b/arch/mips/kernel/cmpxchg.c @@ -22,7 +22,7 @@ unsigned long __xchg_small(volatile void *ptr, unsigned long val, unsigned int s /* * Calculate a shift & mask that correspond to the value we wish to - * exchange within the naturally aligned 4 byte integerthat includes + * exchange within the naturally aligned 4 byte integer that includes * it. */ shift = (unsigned long)ptr & 0x3; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f0ea92937546..d510f628ee03 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -156,7 +156,7 @@ static inline void check_errata(void) /* * Erratum "RPS May Cause Incorrect Instruction Execution" * This code only handles VPE0, any SMP/RTOS code - * making use of VPE1 will be responsable for that VPE. + * making use of VPE1 will be responsible for that VPE. */ if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 146d9fa77f75..53adcc1b2ed5 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -228,7 +228,7 @@ void __init check_wait(void) break; /* - * Another rev is incremeting c0_count at a reduced clock + * Another rev is incrementing c0_count at a reduced clock * rate while in WAIT mode. So we basically have the choice * between using the cp0 timer as clocksource or avoiding * the WAIT instruction. Until more details are known, diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 1641d274fe37..c4d6b09136b1 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -329,7 +329,7 @@ static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, for (i = mipspmu.num_counters - 1; i >= 0; i--) { /* * Note that some MIPS perf events can be counted by both - * even and odd counters, wheresas many other are only by + * even and odd counters, whereas many other are only by * even _or_ odd counters. This introduces an issue that * when the former kind of event takes the counter the * latter kind of event wants to use, then the "counter |