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| author | Greentime Hu <greentime.hu@sifive.com> | 2022-09-13 06:18:17 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-10-13 11:06:56 -0700 |
| commit | da29dbcda49d60f34055df19bd4783b889fc7dfc (patch) | |
| tree | c21a4f5e742f1b098ce0986501bf7c3e08c7a64f /arch/mips/kernel/spinlock_test.c | |
| parent | afc7a5834f0de13aee46df62f09e479c1bbf7b9d (diff) | |
| download | lwn-da29dbcda49d60f34055df19bd4783b889fc7dfc.tar.gz lwn-da29dbcda49d60f34055df19bd4783b889fc7dfc.zip | |
riscv: Add cache information in AUX vector
There are no standard CSR registers to provide cache information, the
way for RISC-V is to get this information from DT. sysconf syscall
could use them to get information of cache through AUX vector.
The result of 'getconf -a|grep -i cache' as follows:
LEVEL1_ICACHE_SIZE 32768
LEVEL1_ICACHE_ASSOC 2
LEVEL1_ICACHE_LINESIZE 64
LEVEL1_DCACHE_SIZE 32768
LEVEL1_DCACHE_ASSOC 4
LEVEL1_DCACHE_LINESIZE 64
LEVEL2_CACHE_SIZE 524288
LEVEL2_CACHE_ASSOC 8
LEVEL2_CACHE_LINESIZE 64
LEVEL3_CACHE_SIZE 4194304
LEVEL3_CACHE_ASSOC 16
LEVEL3_CACHE_LINESIZE 64
LEVEL4_CACHE_SIZE 0
LEVEL4_CACHE_ASSOC 0
LEVEL4_CACHE_LINESIZE 0
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Zong Li <zong.li@sifive.com>
Suggested-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220913061817.22564-8-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/mips/kernel/spinlock_test.c')
0 files changed, 0 insertions, 0 deletions