Merge tag 'mips_4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Paul Burton:
 "Here's the main MIPS pull for Linux 4.21. Core architecture changes
  include:

   - Syscall tables & definitions for unistd.h are now generated by
     scripts, providing greater consistency with other architectures &
     making it easier to add new syscalls.

   - Support for building kernels with no floating point support, upon
     which any userland attempting to use floating point instructions
     will receive a SIGILL. Mostly useful to shrink the kernel & as
     preparation for nanoMIPS support which does not yet include FP.

   - MIPS SIMD Architecture (MSA) vector register context is now exposed
     by ptrace via a new NT_MIPS_MSA regset.

   - ASIDs are now stored as 64b values even for MIPS32 kernels,
     expanding the ASID version field sufficiently that we don't need to
     worry about overflow & avoiding rare issues with reused ASIDs that
     have been observed in the wild.

   - The branch delay slot "emulation" page is now mapped without write
     permission for the user, preventing its use as a nice location for
     attacks to execute malicious code from.

   - Support for ioremap_prot(), primarily to allow gdb or other ptrace
     users the ability to view their tracee's memory using the same
     cache coherency attribute.

   - Optimizations to more cpu_has_* macros, allowing more to be
     compile-time constant where possible.

   - Enable building the whole kernel with UBSAN instrumentation.

   - Enable building the kernel with link-time dead code & data
     elimination.

  Platform specific changes include:

   - The Boston board gains a workaround for DMA prefetching issues with
     the EG20T Platform Controller Hub that it uses.

   - Cleanups to Cavium Octeon code removing about 20k lines of
     redundant code, mostly unused or duplicate register definitions in
     headers.

   - defconfig updates for the DECstation machines, including new
     defconfigs for r4k & 64b machines.

   - Further work on Loongson 3 support.

   - DMA fixes for SiByte machines"

* tag 'mips_4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (95 commits)
  MIPS: math-emu: Write-protect delay slot emulation pages
  MIPS: Remove struct mm_context_t fp_mode_switching field
  mips: generate uapi header and system call table files
  mips: add system call table generation support
  mips: remove syscall table entries
  mips: add +1 to __NR_syscalls in uapi header
  mips: rename scall64-64.S to scall64-n64.S
  mips: remove unused macros
  mips: add __NR_syscalls along with __NR_Linux_syscalls
  MIPS: Expand MIPS32 ASIDs to 64 bits
  MIPS: OCTEON: delete redundant register definitions
  MIPS: OCTEON: cvmx_gmxx_inf_mode: use oldest forward compatible definition
  MIPS: OCTEON: cvmx_mio_fus_dat3: use oldest forward compatible definition
  MIPS: OCTEON: cvmx_pko_mem_debug8: use oldest forward compatible definition
  MIPS: OCTEON: octeon-usb: use common gpio_bit definition
  MIPS: OCTEON: enable all OCTEON drivers in defconfig
  mips: annotate implicit fall throughs
  MIPS: Hardcode cpu_has_mips* where target ISA allows
  MIPS: MT: Remove norps command line parameter
  MIPS: Only include mmzone.h when CONFIG_NEED_MULTIPLE_NODES=y
  ...

1 files changed, 107 insertions, 38 deletions

diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index a2813fe381cf..42bc2bbbd3d7 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -30,13 +30,6 @@
 #include <asm/mips_mt.h>
 #endif
 
-struct sigcontext;
-struct sigcontext32;
-
-extern void _init_fpu(unsigned int);
-extern void _save_fp(struct task_struct *);
-extern void _restore_fp(struct task_struct *);
-
 /*
  * This enum specifies a mode in which we want the FPU to operate, for cores
  * which implement the Status.FR bit. Note that the bottom bit of the value
@@ -51,6 +44,11 @@ enum fpu_mode {
 #define FPU_FR_MASK		0x1
 };
 
+#ifdef CONFIG_MIPS_FP_SUPPORT
+
+extern void _save_fp(struct task_struct *);
+extern void _restore_fp(struct task_struct *);
+
 #define __disable_fpu()							\
 do {									\
 	clear_c0_status(ST0_CU1);					\
@@ -198,42 +196,36 @@ static inline void lose_fpu(int save)
 	preempt_enable();
 }
 
-static inline int init_fpu(void)
+/**
+ * init_fp_ctx() - Initialize task FP context
+ * @target: The task whose FP context should be initialized.
+ *
+ * Initializes the FP context of the target task to sane default values if that
+ * target task does not already have valid FP context. Once the context has
+ * been initialized, the task will be marked as having used FP & thus having
+ * valid FP context.
+ *
+ * Returns: true if context is initialized, else false.
+ */
+static inline bool init_fp_ctx(struct task_struct *target)
 {
-	unsigned int fcr31 = current->thread.fpu.fcr31;
-	int ret = 0;
+	/* If FP has been used then the target already has context */
+	if (tsk_used_math(target))
+		return false;
 
-	if (cpu_has_fpu) {
-		unsigned int config5;
-
-		ret = __own_fpu();
-		if (ret)
-			return ret;
+	/* Begin with data registers set to all 1s... */
+	memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr));
 
-		if (!cpu_has_fre) {
-			_init_fpu(fcr31);
+	/* FCSR has been preset by `mips_set_personality_nan'.  */
 
-			return 0;
-		}
-
-		/*
-		 * Ensure FRE is clear whilst running _init_fpu, since
-		 * single precision FP instructions are used. If FRE
-		 * was set then we'll just end up initialising all 32
-		 * 64b registers.
-		 */
-		config5 = clear_c0_config5(MIPS_CONF5_FRE);
-		enable_fpu_hazard();
+	/*
+	 * Record that the target has "used" math, such that the context
+	 * just initialised, and any modifications made by the caller,
+	 * aren't discarded.
+	 */
+	set_stopped_child_used_math(target);
 
-		_init_fpu(fcr31);
-
-		/* Restore FRE */
-		write_c0_config5(config5);
-		enable_fpu_hazard();
-	} else
-		fpu_emulator_init_fpu();
-
-	return ret;
+	return true;
 }
 
 static inline void save_fp(struct task_struct *tsk)
@@ -260,4 +252,81 @@ static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
 	return tsk->thread.fpu.fpr;
 }
 
+#else /* !CONFIG_MIPS_FP_SUPPORT */
+
+/*
+ * When FP support is disabled we provide only a minimal set of stub functions
+ * to avoid callers needing to care too much about CONFIG_MIPS_FP_SUPPORT.
+ */
+
+static inline int __enable_fpu(enum fpu_mode mode)
+{
+	return SIGILL;
+}
+
+static inline void __disable_fpu(void)
+{
+	/* no-op */
+}
+
+
+static inline int is_fpu_owner(void)
+{
+	return 0;
+}
+
+static inline void clear_fpu_owner(void)
+{
+	/* no-op */
+}
+
+static inline int own_fpu_inatomic(int restore)
+{
+	return SIGILL;
+}
+
+static inline int own_fpu(int restore)
+{
+	return SIGILL;
+}
+
+static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
+{
+	/* no-op */
+}
+
+static inline void lose_fpu(int save)
+{
+	/* no-op */
+}
+
+static inline bool init_fp_ctx(struct task_struct *target)
+{
+	return false;
+}
+
+/*
+ * The following functions should only be called in paths where we know that FP
+ * support is enabled, typically a path where own_fpu() or __enable_fpu() have
+ * returned successfully. When CONFIG_MIPS_FP_SUPPORT=n it is known at compile
+ * time that this should never happen, so calls to these functions should be
+ * optimized away & never actually be emitted.
+ */
+
+extern void save_fp(struct task_struct *tsk)
+	__compiletime_error("save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern void _save_fp(struct task_struct *)
+	__compiletime_error("_save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern void restore_fp(struct task_struct *tsk)
+	__compiletime_error("restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern void _restore_fp(struct task_struct *)
+	__compiletime_error("_restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+extern union fpureg *get_fpu_regs(struct task_struct *tsk)
+	__compiletime_error("get_fpu_regs() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
+
+#endif /* !CONFIG_MIPS_FP_SUPPORT */
 #endif /* _ASM_FPU_H */