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authorChristian Marangi <ansuelsmth@gmail.com>2024-06-20 17:26:44 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2024-06-27 10:44:32 +0200
commitb95b30e50aed225d26e20737873ae2404941901c (patch)
treef2abb3cc75e1ce9a151de76cf6bbf2de091dc660 /arch/mips/bcm63xx/setup.c
parent3de96d810ffd712b7ad2bd764c1390fac2436551 (diff)
downloadlwn-b95b30e50aed225d26e20737873ae2404941901c.tar.gz
lwn-b95b30e50aed225d26e20737873ae2404941901c.zip
mips: bmips: setup: make CBR address configurable
Add support to provide CBR address from DT to handle broken SoC/Bootloader that doesn't correctly init it. This permits to use the RAC flush even in these condition. To provide a CBR address from DT, the property "brcm,bmips-cbr-reg" needs to be set in the "cpus" node. On DT init, this property presence will be checked and will set the bmips_cbr_addr value accordingly. Also bmips_rac_flush_disable will be set to false as RAC flush can be correctly supported. The CBR address from DT will overwrite the cached one and the one set in the CBR register will be ignored. Also the DT CBR address is validated on being outside DRAM window. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/bcm63xx/setup.c')
-rw-r--r--arch/mips/bcm63xx/setup.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 16ea8945ae3a..81529084bc75 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -23,7 +23,11 @@
#include <bcm63xx_io.h>
#include <bcm63xx_gpio.h>
-/* CBR addr doesn't change and we can cache it */
+/*
+ * CBR addr doesn't change and we can cache it.
+ * For broken SoC/Bootloader CBR addr might also be provided via DT
+ * with "brcm,bmips-cbr-reg" in the "cpus" node.
+ */
void __iomem *bmips_cbr_addr __read_mostly;
void bcm63xx_machine_halt(void)