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authorJiri Kosina <jkosina@suse.cz>2013-09-04 10:49:39 +0200
committerJiri Kosina <jkosina@suse.cz>2013-09-04 10:49:57 +0200
commitefd15f5f4ff63f6ac5d80850686e3d2cc8c4481b (patch)
tree40024adbe77a3d660662e639fd765097133d648c /arch/mips/bcm63xx/cpu.c
parent6c2794a2984f4c17a58117a68703cc7640f01c5a (diff)
parent58c59bc997d86593f0bea41845885917cf304d22 (diff)
downloadlwn-efd15f5f4ff63f6ac5d80850686e3d2cc8c4481b.tar.gz
lwn-efd15f5f4ff63f6ac5d80850686e3d2cc8c4481b.zip
Merge branch 'master' into for-3.12/upstream
Sync with Linus' tree to be able to apply fixup patch on top of 9d9a04ee75 ("HID: apple: Add support for the 2013 Macbook Air") Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'arch/mips/bcm63xx/cpu.c')
-rw-r--r--arch/mips/bcm63xx/cpu.c28
1 files changed, 25 insertions, 3 deletions
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 79fe32df5e96..7e17374a9ae8 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,6 +29,14 @@ static u8 bcm63xx_cpu_rev;
static unsigned int bcm63xx_cpu_freq;
static unsigned int bcm63xx_memory_size;
+static const unsigned long bcm3368_regs_base[] = {
+ __GEN_CPU_REGS_TABLE(3368)
+};
+
+static const int bcm3368_irqs[] = {
+ __GEN_CPU_IRQ_TABLE(3368)
+};
+
static const unsigned long bcm6328_regs_base[] = {
__GEN_CPU_REGS_TABLE(6328)
};
@@ -116,6 +124,9 @@ unsigned int bcm63xx_get_memory_size(void)
static unsigned int detect_cpu_clock(void)
{
switch (bcm63xx_get_cpu_id()) {
+ case BCM3368_CPU_ID:
+ return 300000000;
+
case BCM6328_CPU_ID:
{
unsigned int tmp, mips_pll_fcvo;
@@ -266,7 +277,7 @@ static unsigned int detect_memory_size(void)
banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
}
- if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+ if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
val = bcm_memc_readl(MEMC_CFG_REG);
rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -302,10 +313,17 @@ void __init bcm63xx_cpu_init(void)
chipid_reg = BCM_6345_PERF_BASE;
break;
case CPU_BMIPS4350:
- if ((read_c0_prid() & 0xf0) == 0x10)
+ switch ((read_c0_prid() & 0xff)) {
+ case 0x04:
+ chipid_reg = BCM_3368_PERF_BASE;
+ break;
+ case 0x10:
chipid_reg = BCM_6345_PERF_BASE;
- else
+ break;
+ default:
chipid_reg = BCM_6368_PERF_BASE;
+ break;
+ }
break;
}
@@ -322,6 +340,10 @@ void __init bcm63xx_cpu_init(void)
bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
switch (bcm63xx_cpu_id) {
+ case BCM3368_CPU_ID:
+ bcm63xx_regs_base = bcm3368_regs_base;
+ bcm63xx_irqs = bcm3368_irqs;
+ break;
case BCM6328_CPU_ID:
bcm63xx_regs_base = bcm6328_regs_base;
bcm63xx_irqs = bcm6328_irqs;