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| author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2008-03-27 16:09:31 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-04-01 15:46:34 +0100 |
| commit | 758e285faca4db948ecddefb523007255b29cdb7 (patch) | |
| tree | 530fb34442234b04afe0972d6765bbc7f17ba0f6 /arch/mips/au1000/common/time.c | |
| parent | b1ec4c8e483d0d00d3114eafdb2c85c1cf3ed4ae (diff) | |
| download | lwn-758e285faca4db948ecddefb523007255b29cdb7.tar.gz lwn-758e285faca4db948ecddefb523007255b29cdb7.zip | |
[MIPS] Alchemy: work around clock misdetection on early Au1000
Work around the CPU clock miscalculation on Au1000DA/HA/HB due the
sys_cpupll register being write-only, i.e. actually do what the comment
before cal_r4off() function advertised for years but the code failed at.
This is achieved by just giving user a chance to define the clock
explicitly in the board config. via CONFIG_SOC_AU1000_FREQUENCY option,
defaulting to 396 MHz if the option is not given...
The patch is based on the AMD's big unpublished patch, the issue seems to
be an undocumented errata (or feature :-)...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/au1000/common/time.c')
| -rw-r--r-- | arch/mips/au1000/common/time.c | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index f113b512d7b1..e122bbc6cd88 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -209,18 +209,22 @@ unsigned long cal_r4koff(void) while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); au_writel(0, SYS_TOYWRITE); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); + } else + no_au1xxx_32khz = 1; - cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * - AU1000_SRC_CLK; - } - else { - /* The 32KHz oscillator isn't running, so assume there - * isn't one and grab the processor speed from the PLL. - * NOTE: some old silicon doesn't allow reading the PLL. - */ + /* + * On early Au1000, sys_cpupll was write-only. Since these + * silicon versions of Au1000 are not sold by AMD, we don't bend + * over backwards trying to determine the frequency. + */ + if (cur_cpu_spec[0]->cpu_pll_wo) +#ifdef CONFIG_SOC_AU1000_FREQUENCY + cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; +#else + cpu_speed = 396000000; +#endif + else cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; - no_au1xxx_32khz = 1; - } mips_hpt_frequency = cpu_speed; // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16)); |