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| author | Wu Zhangjin <wuzhangjin@gmail.com> | 2009-11-06 18:45:05 +0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-12-17 01:57:10 +0000 |
| commit | 6f7a251a259e5bf58a9ff334bdcfa3e42b6cb7a3 (patch) | |
| tree | f5b65babda54c52073819629cc0f1047b5d1b413 /arch/mips/Kconfig | |
| parent | 937893cf5be53203eabc6f4db29f86b1fdeea203 (diff) | |
| download | lwn-6f7a251a259e5bf58a9ff334bdcfa3e42b6cb7a3.tar.gz lwn-6f7a251a259e5bf58a9ff334bdcfa3e42b6cb7a3.zip | |
MIPS: Loongson: Add basic Loongson 2F support
Loongson 2F has built-in DDR2 and PCI-X controller. The PCI-X controller
has a programming interface similiar to the the FPGA northbridge used on
Loongson 2E.
The main differences between Loongson 2E and Loongson 2F include:
1. Loongson 2F has an extra address window configuration module, which
is used to map CPU address space to DDR or PCI address space, or map
the PCI-DMA address space to DDR or LIO address space.
2. Loongson 2F supports 8 levels of software configurable CPu frequency
which can be configured in the LOONGSON_CHIPCFG0 register. The coming
cpufreq and standby support are based on this feature.
Loongson.h abstracts the modules and corresponding methods are abstracted.
Add other Loongson-2F-specific source code including gcc 4.4 support, PCI
memory space, PCI IO space, DMA address.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a16b6dfe3bc3..9618451011e1 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1073,6 +1073,21 @@ config CPU_LOONGSON2E The Loongson 2E processor implements the MIPS III instruction set with many extensions. + It has an internal FPGA northbridge, which is compatiable to + bonito64. + +config CPU_LOONGSON2F + bool "Loongson 2F" + depends on SYS_HAS_CPU_LOONGSON2F + select CPU_LOONGSON2 + help + The Loongson 2F processor implements the MIPS III instruction set + with many extensions. + + Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller + have a similar programming interface with FPGA northbridge used in + Loongson2E. + config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1 @@ -1317,6 +1332,9 @@ config CPU_LOONGSON2 config SYS_HAS_CPU_LOONGSON2E bool +config SYS_HAS_CPU_LOONGSON2F + bool + config SYS_HAS_CPU_MIPS32_R1 bool |