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| author | Greg Ungerer <gerg@uclinux.org> | 2009-05-19 14:38:08 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2009-09-16 09:43:50 +1000 |
| commit | f2154bef817ac3d0ea67b52526fd8e88898b66f9 (patch) | |
| tree | 3ffa5cf5c3ec82a59f75728a580bd9332a32ebee /arch/m68k/include/asm/m5249sim.h | |
| parent | 5187995f0a9253e915dfee83684eae7b692213e6 (diff) | |
| download | lwn-f2154bef817ac3d0ea67b52526fd8e88898b66f9.tar.gz lwn-f2154bef817ac3d0ea67b52526fd8e88898b66f9.zip | |
m68knommu: merge old ColdFire interrupt controller masking macros
Currently the code that supports setting the old style ColdFire interrupt
controller mask registers is macros in the include files of each of the
CPU types. Merge all these into a set of real masking functions in the
old Coldfire interrupt controller code proper. All the macros are basically
the same (excepting a register size difference on really early parts).
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m5249sim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5249sim.h | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 2c23a83512a4..36ed31bbf6cb 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h @@ -106,19 +106,6 @@ #define MCFGPIO_PIN_MAX 64 #define MCFGPIO_IRQ_MAX -1 #define MCFGPIO_IRQ_VECBASE -1 -/* - * Macro to set IMR register. It is 32 bits on the 5249. - */ -#define MCFSIM_IMR_MASKALL 0x7fffe /* All SIM intr sources */ - -#define mcf_getimr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) - -#define mcf_setimr(imr) \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); - -#define mcf_getipr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) /****************************************************************************/ |