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author | Jianmin Lv <lvjianmin@loongson.cn> | 2022-07-14 20:42:16 +0800 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-07-21 12:42:00 -0500 |
commit | 930c6074d7dd579f3d4e8b04548dd8cb0341de1d (patch) | |
tree | 6f7c1ad247f2c92652f70b2064ac1be3abd39b41 /arch/loongarch/include | |
parent | 2410e3301fcc40f6ebda234928c66a22f4257d9f (diff) | |
download | lwn-930c6074d7dd579f3d4e8b04548dd8cb0341de1d.tar.gz lwn-930c6074d7dd579f3d4e8b04548dd8cb0341de1d.zip |
PCI: loongson: Work around LS7A incorrect Interrupt Pin registers
Several devices integrated into LS7A report 1 (which means they use
INTA) in their Interrupt Pin registers, but they actually use a different
interrupt.
Add a quirk to override the incorrect Interrupt Pin values.
This is only needed by ACPI-based systems. For DT-based systems,
pci_assign_irq() ignores the Interrupt Pin register except to learn that
the device uses INTx and the host bridge .map_irq() function
(loongson_map_irq()) learns the IRQ mapping via DT and of_irq_parse_pci().
[bhelgaas: drop PCIE_PORT_x, OHCI, GPU since they are function 0 and don't
need the quirk, squash in updates from
https://lore.kernel.org/r/CAAhV-H40_o+9KS1t67O98GusM38pDaiB4bssxd3KQZpAByfnLg@mail.gmail.com]
Link: https://lore.kernel.org/r/20220714124216.1489304-8-chenhuacai@loongson.cn
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'arch/loongarch/include')
0 files changed, 0 insertions, 0 deletions