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| author | Huacai Chen <chenhuacai@loongson.cn> | 2023-06-29 20:58:43 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2023-06-29 20:58:43 +0800 |
| commit | f6f0c9a74a48448583c3cb0f3f067bc3fe0f13c6 (patch) | |
| tree | e31359d5a5de9d228a03ba15ca70a3855586c902 /arch/loongarch/include/asm/cpu-info.h | |
| parent | 616500232e632dba8b03981eeccadacf2fbf1c30 (diff) | |
| download | lwn-f6f0c9a74a48448583c3cb0f3f067bc3fe0f13c6.tar.gz lwn-f6f0c9a74a48448583c3cb0f3f067bc3fe0f13c6.zip | |
LoongArch: Add SMT (Simultaneous Multi-Threading) support
Loongson-3A6000 has SMT (Simultaneous Multi-Threading) support, each
physical core has two logical cores (threads). This patch add SMT probe
and scheduler support via ACPI PPTT.
If SCHED_SMT enabled, Loongson-3A6000 is treated as 4 cores, 8 threads;
If SCHED_SMT disabled, Loongson-3A6000 is treated as 8 cores, 8 threads.
Remove smp_num_siblings to support HMP (Heterogeneous Multi-Processing).
Signed-off-by: Liupu Wang <wangliupu@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/include/asm/cpu-info.h')
| -rw-r--r-- | arch/loongarch/include/asm/cpu-info.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/loongarch/include/asm/cpu-info.h b/arch/loongarch/include/asm/cpu-info.h index cd73a6f57fe3..900589cb159d 100644 --- a/arch/loongarch/include/asm/cpu-info.h +++ b/arch/loongarch/include/asm/cpu-info.h @@ -54,6 +54,7 @@ struct cpuinfo_loongarch { struct cache_desc cache_leaves[CACHE_LEAVES_MAX]; int core; /* physical core number in package */ int package;/* physical package number */ + int global_id; /* physical global thread number */ int vabits; /* Virtual Address size in bits */ int pabits; /* Physical Address size in bits */ unsigned int ksave_mask; /* Usable KSave mask. */ |