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| author | Al Viro <viro@zeniv.linux.org.uk> | 2020-07-11 00:12:07 -0400 |
|---|---|---|
| committer | Al Viro <viro@zeniv.linux.org.uk> | 2020-08-20 15:45:14 -0400 |
| commit | cc44c17baf7f3f833d36b2f2a1edb1cc0b6f2cc4 (patch) | |
| tree | 78e1d7c77dfd8cc862ba559d4c4c6653a5002c1b /arch/c6x | |
| parent | 6e41c585e38ff696de3a11509a0ad0a11150b0c3 (diff) | |
| download | lwn-cc44c17baf7f3f833d36b2f2a1edb1cc0b6f2cc4.tar.gz lwn-cc44c17baf7f3f833d36b2f2a1edb1cc0b6f2cc4.zip | |
csum_partial_copy_nocheck(): drop the last argument
It's always 0. Note that we theoretically could use ~0U as well -
result will be the same modulo 0xffff, _if_ the damn thing did the
right thing for any value of initial sum; later we'll make use of
that when convenient.
However, unlike csum_and_copy_..._user(), there are instances that
did not work for arbitrary initial sums; c6x is one such.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Diffstat (limited to 'arch/c6x')
| -rw-r--r-- | arch/c6x/include/asm/checksum.h | 2 | ||||
| -rw-r--r-- | arch/c6x/lib/csum_64plus.S | 4 |
2 files changed, 2 insertions, 4 deletions
diff --git a/arch/c6x/include/asm/checksum.h b/arch/c6x/include/asm/checksum.h index fa31bdc186b2..934918def632 100644 --- a/arch/c6x/include/asm/checksum.h +++ b/arch/c6x/include/asm/checksum.h @@ -27,7 +27,7 @@ csum_tcpudp_nofold(__be32 saddr, __be32 daddr, __u32 len, #define csum_tcpudp_nofold csum_tcpudp_nofold #define _HAVE_ARCH_CSUM_AND_COPY -extern __wsum csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum); +extern __wsum csum_partial_copy_nocheck(const void *src, void *dst, int len); #include <asm-generic/checksum.h> diff --git a/arch/c6x/lib/csum_64plus.S b/arch/c6x/lib/csum_64plus.S index 9c07127485d1..57148866d8d3 100644 --- a/arch/c6x/lib/csum_64plus.S +++ b/arch/c6x/lib/csum_64plus.S @@ -24,7 +24,6 @@ ENTRY(csum_partial_copy_nocheck) MVC .S2 ILC,B30 - MV .D1X B6,A31 ; given csum ZERO .D1 A9 ; csum (a side) || ZERO .D2 B9 ; csum (b side) || SHRU .S2X A6,2,B5 ; len / 4 @@ -144,8 +143,7 @@ L91: SHRU .S2X A9,16,B4 SHRU .S1 A9,16,A0 [A0] BNOP .S1 L91,5 -L10: ADD .D1 A31,A9,A9 - MV .D1 A9,A4 +L10: MV .D1 A9,A4 BNOP .S2 B3,4 MVC .S2 B30,ILC |