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author | Arnd Bergmann <arnd@arndb.de> | 2022-05-27 22:20:31 +0200 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2022-05-27 22:20:32 +0200 |
commit | 440517772bec24f618ec98bc608024ad1b37e80f (patch) | |
tree | 5567c8e7eb5af9f2e7b18526494a42a7a7137344 /arch/arm | |
parent | 4a4e81ddb8b0eb412bcfb90c24ba0d5d0d913483 (diff) | |
parent | 840fc447d78e3d4e4048c307ec8f6649d2abb9e7 (diff) | |
download | lwn-440517772bec24f618ec98bc608024ad1b37e80f.tar.gz lwn-440517772bec24f618ec98bc608024ad1b37e80f.zip |
Merge tag 'v5.19-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/late
Amba and clock fixes to conform better to actual dt-bindings.
* tag 'v5.19-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: add clocks property to cru node rk3228
ARM: dts: rockchip: add clocks property to cru node rk3036
ARM: dts: rockchip: add clocks property to cru node rk3066a/rk3188
ARM: dts: rockchip: add clocks property to cru node rk3288
ARM: dts: rockchip: Remove "amba" bus nodes from rv1108
ARM: dts: rockchip: add clocks property to cru node rv1108
Link: https://lore.kernel.org/r/4798587.jE0xQCEvom@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/boot/dts/rk3036.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/boot/dts/rk3066a.dtsi | 3 | ||||
-rw-r--r-- | arch/arm/boot/dts/rk3188.dtsi | 3 | ||||
-rw-r--r-- | arch/arm/boot/dts/rk322x.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/boot/dts/rv1108.dtsi | 31 |
6 files changed, 23 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 242ce42fbd87..9b0f0497567d 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -330,6 +330,8 @@ cru: clock-controller@20000000 { compatible = "rockchip,rk3036-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index c25b9695db4b..de9915d946f7 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -202,8 +202,9 @@ cru: clock-controller@20000000 { compatible = "rockchip,rk3066a-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; - #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index a94321e90014..cdd4a0bd5133 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -195,8 +195,9 @@ cru: clock-controller@20000000 { compatible = "rockchip,rk3188-cru"; reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; - #clock-cells = <1>; #reset-cells = <1>; }; diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 6513ffcaac92..ffc16d6b97e1 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -484,6 +484,8 @@ cru: clock-controller@110e0000 { compatible = "rockchip,rk3228-cru"; reg = <0x110e0000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 26b9bbe310af..487b0e03d4b4 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -862,6 +862,8 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3288-cru"; reg = <0x0 0xff760000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 448254906452..c158a7ea86ec 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -85,24 +85,6 @@ #clock-cells = <0>; }; - amba: bus { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@102a0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x102a0000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - bus_intmem: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x2000>; @@ -259,6 +241,17 @@ status = "disabled"; }; + pdma: dma-controller@102a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x102a0000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + grf: syscon@10300000 { compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; reg = <0x10300000 0x1000>; @@ -456,6 +449,8 @@ cru: clock-controller@20200000 { compatible = "rockchip,rv1108-cru"; reg = <0x20200000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; |