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author | Kristina Martsenko <kristina.martsenko@arm.com> | 2017-11-16 17:58:20 +0000 |
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committer | Christoffer Dall <christoffer.dall@linaro.org> | 2017-11-29 16:46:17 +0100 |
commit | 26aa7b3b1c0fb3f1a6176a0c1847204ef4355693 (patch) | |
tree | f2b73981eae7b25aa9a1fc3a407f5739afe5c844 /arch/arm | |
parent | a05d1c0d03fd60ed487991e73850421e735c0135 (diff) | |
download | lwn-26aa7b3b1c0fb3f1a6176a0c1847204ef4355693.tar.gz lwn-26aa7b3b1c0fb3f1a6176a0c1847204ef4355693.zip |
arm64: KVM: fix VTTBR_BADDR_MASK BUG_ON off-by-one
VTTBR_BADDR_MASK is used to sanity check the size and alignment of the
VTTBR address. It seems to currently be off by one, thereby only
allowing up to 47-bit addresses (instead of 48-bit) and also
insufficiently checking the alignment. This patch fixes it.
As an example, with 4k pages, before this patch we have:
PHYS_MASK_SHIFT = 48
VTTBR_X = 37 - 24 = 13
VTTBR_BADDR_SHIFT = 13 - 1 = 12
VTTBR_BADDR_MASK = ((1 << 35) - 1) << 12 = 0x00007ffffffff000
Which is wrong, because the mask doesn't allow bit 47 of the VTTBR
address to be set, and only requires the address to be 12-bit (4k)
aligned, while it actually needs to be 13-bit (8k) aligned because we
concatenate two 4k tables.
With this patch, the mask becomes 0x0000ffffffffe000, which is what we
want.
Fixes: 0369f6a34b9f ("arm64: KVM: EL2 register definitions")
Cc: <stable@vger.kernel.org> # 3.11.x
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'arch/arm')
0 files changed, 0 insertions, 0 deletions