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| author | Will Deacon <will.deacon@arm.com> | 2015-08-20 11:47:13 +0100 |
|---|---|---|
| committer | Sasha Levin <sasha.levin@oracle.com> | 2016-02-01 12:22:03 -0500 |
| commit | 1d4c425164b922424b3f86f93f3f0b7f85293fa7 (patch) | |
| tree | 8928f06936e1c555312a8bce96d5bfcb23c1c267 /arch/arm64 | |
| parent | e70aade221a271f91e2d71901b2d602df2faee15 (diff) | |
| download | lwn-1d4c425164b922424b3f86f93f3f0b7f85293fa7.tar.gz lwn-1d4c425164b922424b3f86f93f3f0b7f85293fa7.zip | |
arm64: mdscr_el1: avoid exposing DCC to userspace
[ Upstream commit d8d23fa0f27f3b2942a7bbc7378c7735324ed519 ]
We don't want to expose the DCC to userspace, particularly as there is
a kernel console driver for it.
This patch resets mdscr_el1 to disable userspace access to the DCC
registers on the cold boot path.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/mm/proc.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index cdd754e19b9b..d2c2e3b6c0f9 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -202,7 +202,8 @@ ENTRY(__cpu_setup) mov x0, #3 << 20 msr cpacr_el1, x0 // Enable FP/ASIMD - msr mdscr_el1, xzr // Reset mdscr_el1 + mov x0, #1 << 12 // Reset mdscr_el1 and disable + msr mdscr_el1, x0 // access to the DCC from EL0 /* * Memory region attributes for LPAE: * |