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| author | Alexandru Elisei <alexandru.elisei@arm.com> | 2020-09-15 18:04:42 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2020-09-18 16:18:24 +0100 |
| commit | ada329e6b5b406f33fae665e62caff7814409906 (patch) | |
| tree | 3f8ccb7a0cf659f19c2e49cb8e00177418895190 /arch/arm64/kvm | |
| parent | 523b3999e5f620cb5ccce6a7ca2780a4cab579a2 (diff) | |
| download | lwn-ada329e6b5b406f33fae665e62caff7814409906.tar.gz lwn-ada329e6b5b406f33fae665e62caff7814409906.zip | |
KVM: arm64: Do not flush memslot if FWB is supported
As a result of a KVM_SET_USER_MEMORY_REGION ioctl, KVM flushes the
dcache for the memslot being changed to ensure a consistent view of memory
between the host and the guest: the host runs with caches enabled, and
it is possible for the data written by the hypervisor to still be in the
caches, but the guest is running with stage 1 disabled, meaning data
accesses are to Device-nGnRnE memory, bypassing the caches entirely.
Flushing the dcache is not necessary when KVM enables FWB, because it
forces the guest to uses cacheable memory accesses.
The current behaviour does not change, as the dcache flush helpers execute
the cache operation only if FWB is not enabled, but walking the stage 2
table is avoided.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200915170442.131635-1-alexandru.elisei@arm.com
Diffstat (limited to 'arch/arm64/kvm')
| -rw-r--r-- | arch/arm64/kvm/mmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 852497bd6d1e..4d68c160a7b5 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1344,7 +1344,7 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, spin_lock(&kvm->mmu_lock); if (ret) unmap_stage2_range(&kvm->arch.mmu, mem->guest_phys_addr, mem->memory_size); - else + else if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) stage2_flush_memslot(kvm, memslot); spin_unlock(&kvm->mmu_lock); out: |