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authorMarc Zyngier <maz@kernel.org>2025-01-27 11:58:38 +0000
committerMarc Zyngier <maz@kernel.org>2025-05-10 11:04:35 +0100
commit397411c743c77a9c1d90f407b502010227a259dc (patch)
treec22900c262a0122e99f3c5b9d09d64060ae437b7 /arch/arm64/kvm/handle_exit.c
parentef6d7d2682d948df217db73985e0a159305c7743 (diff)
downloadlwn-397411c743c77a9c1d90f407b502010227a259dc.tar.gz
lwn-397411c743c77a9c1d90f407b502010227a259dc.zip
KVM: arm64: Handle PSB CSYNC traps
The architecture introduces a trap for PSB CSYNC that fits in the same EC as LS64. Let's deal with it in a similar way as LS64. It's not that we expect this to be useful any time soon anyway. Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'arch/arm64/kvm/handle_exit.c')
-rw-r--r--arch/arm64/kvm/handle_exit.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index cc5c2eeebab3..cc44ee56e512 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -347,6 +347,11 @@ static int handle_other(struct kvm_vcpu *vcpu)
if (is_l2)
fwd = !(hcrx & HCRX_EL2_EnALS);
break;
+ case ESR_ELx_ISS_OTHER_PSBCSYNC:
+ allowed = kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P5);
+ if (is_l2)
+ fwd = (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_PSBCSYNC);
+ break;
default:
/* Clearly, we're missing something. */
WARN_ON_ONCE(1);