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authorCatalin Marinas <catalin.marinas@arm.com>2013-09-16 15:19:27 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2014-05-09 15:47:49 +0100
commit15af1942dd61ee236a48b3de14d6f31c0b9e8116 (patch)
treed4f0163789eff325e8fd5088a70592abc3186c14 /arch/arm64/kernel/signal.c
parent0e0276d1e1dd063cd14ce377707970d0417a0792 (diff)
downloadlwn-15af1942dd61ee236a48b3de14d6f31c0b9e8116.tar.gz
lwn-15af1942dd61ee236a48b3de14d6f31c0b9e8116.zip
arm64: Expose ESR_EL1 information to user when SIGSEGV/SIGBUS
This information is useful for instruction emulators to detect read/write and access size without having to decode the faulting instruction. The current patch exports it via sigcontext (struct esr_context) and is only valid for SIGSEGV and SIGBUS. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel/signal.c')
-rw-r--r--arch/arm64/kernel/signal.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index 7ff2eee96c6b..dc2ab1b0ac0d 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -194,6 +194,16 @@ static int setup_sigframe(struct rt_sigframe __user *sf,
aux += sizeof(*fpsimd_ctx);
}
+ /* fault information, if valid */
+ if (current->thread.fault_code) {
+ struct esr_context *esr_ctx =
+ container_of(aux, struct esr_context, head);
+ __put_user_error(ESR_MAGIC, &esr_ctx->head.magic, err);
+ __put_user_error(sizeof(*esr_ctx), &esr_ctx->head.size, err);
+ __put_user_error(current->thread.fault_code, &esr_ctx->esr, err);
+ aux += sizeof(*esr_ctx);
+ }
+
/* set the "end" magic */
end = aux;
__put_user_error(0, &end->magic, err);