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| author | Robert Richter <rrichter@cavium.com> | 2017-01-13 14:12:09 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2017-01-13 13:15:52 +0000 |
| commit | fa5ce3d1928c441c3d241c34a00c07c8f5880b1a (patch) | |
| tree | c68dfdc1a82d2e7c8d0688e193adc1c2d7a1e7ed /arch/arm64/kernel/cpufeature.c | |
| parent | eac8017f0c4719d30f89d1a247de7bfbf6d0da4f (diff) | |
| download | lwn-fa5ce3d1928c441c3d241c34a00c07c8f5880b1a.tar.gz lwn-fa5ce3d1928c441c3d241c34a00c07c8f5880b1a.zip | |
arm64: errata: Provide macro for major and minor cpu revisions
Definition of cpu ranges are hard to read if the cpu variant is not
zero. Provide MIDR_CPU_VAR_REV() macro to describe the full hardware
revision of a cpu including variant and (minor) revision.
Signed-off-by: Robert Richter <rrichter@cavium.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel/cpufeature.c')
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index a995aae59056..ed675061dda0 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -730,13 +730,11 @@ static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) { u32 midr = read_cpuid_id(); - u32 rv_min, rv_max; /* Cavium ThunderX pass 1.x and 2.x */ - rv_min = 0; - rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK; - - return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max); + return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, + MIDR_CPU_VAR_REV(0, 0), + MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); } static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) |