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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-03-06 17:15:35 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-03-09 13:23:09 +0000 |
| commit | ca79acca273630935f2cfdfdf3fc7425ff51ce1c (patch) | |
| tree | eb7562df51b97cc6e33b494c9d744744f6dd4a89 /arch/arm64/kernel/cpu_errata.c | |
| parent | e8002e02abf052c07bb87b867789034bc79aac10 (diff) | |
| download | lwn-ca79acca273630935f2cfdfdf3fc7425ff51ce1c.tar.gz lwn-ca79acca273630935f2cfdfdf3fc7425ff51ce1c.zip | |
arm64/kernel: enable A53 erratum #8434319 handling at runtime
Omit patching of ADRP instruction at module load time if the current
CPUs are not susceptible to the erratum.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
[will: Drop duplicate initialisation of .def_scope field]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel/cpu_errata.c')
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index b161abdd6e27..186c0fc61dcd 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -298,6 +298,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_CPU_VAR_REV(1, 2)), }, #endif +#ifdef CONFIG_ARM64_ERRATUM_843419 + { + /* Cortex-A53 r0p[01234] */ + .desc = "ARM erratum 843419", + .capability = ARM64_WORKAROUND_843419, + MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), + MIDR_FIXED(0x4, BIT(8)), + }, +#endif #ifdef CONFIG_ARM64_ERRATUM_845719 { /* Cortex-A53 r0p[01234] */ |