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| author | Brian Norris <briannorris@chromium.org> | 2017-11-29 15:35:41 -0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-12-04 10:57:11 +0100 |
| commit | 3813a10a5a70f3bb38272f3d8473baf909af0a99 (patch) | |
| tree | b40854d63c92c7efd475364d42b99a326f323a63 /arch/arm64/boot/dts/rockchip/rk3399.dtsi | |
| parent | 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff) | |
| download | lwn-3813a10a5a70f3bb38272f3d8473baf909af0a99.tar.gz lwn-3813a10a5a70f3bb38272f3d8473baf909af0a99.zip | |
arm64: dts: rockchip: add rk3399 DSI0 reset
We've documented this one already, but we didn't add it to the DTSI yet.
Suggested-by: Nickey Yang <nickey.yang@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d340b58ab184..faf8c90bdc1a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1648,6 +1648,8 @@ <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; clock-names = "ref", "pclk", "phy_cfg", "grf"; power-domains = <&power RK3399_PD_VIO>; + resets = <&cru SRST_P_MIPI_DSI0>; + reset-names = "apb"; rockchip,grf = <&grf>; status = "disabled"; |