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| author | Shawn Lin <shawn.lin@rock-chips.com> | 2018-02-09 16:51:48 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2018-02-12 09:39:01 +0100 |
| commit | 2b7d2ed1af2e2c0c90a1a8b97926b7b6c6cb03ed (patch) | |
| tree | b71fb02170d5a3ac7260f49dc27cca3b7ef20ce0 /arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | |
| parent | 73e42e18669934fa96cf2bb54291da54177076d7 (diff) | |
| download | lwn-2b7d2ed1af2e2c0c90a1a8b97926b7b6c6cb03ed.tar.gz lwn-2b7d2ed1af2e2c0c90a1a8b97926b7b6c6cb03ed.zip | |
arm64: dts: rockchip: correct ep-gpios for rk3399-sapphire
The endpoint control gpio for rk3399-sapphire boards is gpio2_a4,
so correct it now.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 0f873c897d0d..ce592a4c0c4c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -457,7 +457,7 @@ assigned-clocks = <&cru SCLK_PCIEPHY_REF>; assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; assigned-clock-rates = <100000000>; - ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; num-lanes = <4>; pinctrl-names = "default"; pinctrl-0 = <&pcie_clkreqn_cpm>; |