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| author | Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> | 2026-03-13 17:27:10 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-03-26 09:40:38 -0500 |
| commit | bba8d9ba7df8f6592552377049fc84958fd0575a (patch) | |
| tree | 40759ae8b2c23fa36692c1232a5dbdf1b70399b9 /arch/arm64/boot/dts/qcom/monaco.dtsi | |
| parent | 85a6cf5ef8cf6e6de948fbba56101fa05049417f (diff) | |
| download | lwn-bba8d9ba7df8f6592552377049fc84958fd0575a.tar.gz lwn-bba8d9ba7df8f6592552377049fc84958fd0575a.zip | |
arm64: dts: qcom: monaco: correct Iris corners for the MXC rail
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always
match the PLL corners on the MXC rail. Correct the performance corners
for the MXC rail following the PLL documentation.
Fixes: bf6ec39c3f36 ("arm64: dts: qcom: qcs8300: add video node")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-3-32a393c25dda@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/monaco.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/monaco.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 2ac600854fb3..0fd3168d0f62 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5312,19 +5312,19 @@ opp-444000000 { opp-hz = /bits/ 64 <444000000>; - required-opps = <&rpmhpd_opp_nom>, + required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_nom>; }; opp-533000000 { opp-hz = /bits/ 64 <533000000>; - required-opps = <&rpmhpd_opp_turbo>, + required-opps = <&rpmhpd_opp_nom>, <&rpmhpd_opp_turbo>; }; opp-560000000 { opp-hz = /bits/ 64 <560000000>; - required-opps = <&rpmhpd_opp_turbo_l1>, + required-opps = <&rpmhpd_opp_nom>, <&rpmhpd_opp_turbo_l1>; }; }; |