diff options
| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-01-02 10:46:29 +0100 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-01-18 17:58:10 -0600 |
| commit | 6db9ed9a128cbae1423d043f3debd8bfa77783fd (patch) | |
| tree | 789c4942af725189afcdaac2f42796dacb9e5ff0 /arch/arm64/boot/dts/qcom/ipq6018.dtsi | |
| parent | 2c6e322a41c5e1ca45be50b9d5fbcda62dc23a0d (diff) | |
| download | lwn-6db9ed9a128cbae1423d043f3debd8bfa77783fd.tar.gz lwn-6db9ed9a128cbae1423d043f3debd8bfa77783fd.zip | |
arm64: dts: qcom: ipq6018: Add/remove some newlines
Some lines were broken very aggresively, presumably to fit under 80 chars
and some places could have used a newline, particularly between subsequent
nodes. Address all that and remove redundant comments near PCIe ranges
while at it so as not to exceed 100 chars needlessly.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
Diffstat (limited to 'arch/arm64/boot/dts/qcom/ipq6018.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 8937b10748f3..0d9074b3b1a2 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -102,26 +102,31 @@ opp-microvolt = <725000>; clock-latency-ns = <200000>; }; + opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-microvolt = <787500>; clock-latency-ns = <200000>; }; + opp-1320000000 { opp-hz = /bits/ 64 <1320000000>; opp-microvolt = <862500>; clock-latency-ns = <200000>; }; + opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; opp-microvolt = <925000>; clock-latency-ns = <200000>; }; + opp-1608000000 { opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <987500>; clock-latency-ns = <200000>; }; + opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <1062500>; @@ -131,8 +136,7 @@ pmuv8: pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; psci: psci { @@ -734,24 +738,18 @@ phys = <&pcie_phy0>; phy-names = "pciephy"; - ranges = <0x81000000 0 0x20200000 0 0x20200000 - 0 0x10000>, /* downstream I/O */ - <0x82000000 0 0x20220000 0 0x20220000 - 0 0xfde0000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>, + <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 75 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 78 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 79 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 83 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, <&gcc GCC_PCIE0_AXI_M_CLK>, |