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| author | Ashish Mhetre <amhetre@nvidia.com> | 2022-04-26 13:08:27 +0530 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2022-04-29 10:36:01 +0200 |
| commit | 000b99e5ed1c9e33c14f3582474ae55cd739ae8d (patch) | |
| tree | 62bcf1ecbeffd79a197709a33801cdc7227ffe03 /arch/arm64/boot/dts/nvidia/tegra186.dtsi | |
| parent | 261a46a977c6babde207d5e979fe5cf779b067b9 (diff) | |
| download | lwn-000b99e5ed1c9e33c14f3582474ae55cd739ae8d.tar.gz lwn-000b99e5ed1c9e33c14f3582474ae55cd739ae8d.zip | |
arm64: tegra: Add memory controller channels
From tegra186 onwards, memory controller support multiple channels.
During the error interrupts from memory controller, corresponding
channels need to be accessed for logging error info and clearing the
interrupt.
So add address and size of these channels in device tree node of
tegra186, tegra194 and tegra234 memory controller. Also add reg-names
for each of these reg items which are used by driver for mapping.
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra186.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 2e7faa1e0b9c..0e9afc3e2f26 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -528,7 +528,13 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; |