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| author | Beniamin Sandu <beniaminsandu@gmail.com> | 2024-05-15 19:12:49 +0100 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2024-05-31 17:04:12 -0500 |
| commit | 1536dc8edc653e0e4a333035a73ff146d0517749 (patch) | |
| tree | 1a62505ed040a830e4a35f014cb085b6d595415f /arch/arm64/boot/dts/altera | |
| parent | 32cdf4c75fdd135e66e11383aa84687873b77b89 (diff) | |
| download | lwn-1536dc8edc653e0e4a333035a73ff146d0517749.tar.gz lwn-1536dc8edc653e0e4a333035a73ff146d0517749.zip | |
arm64: dts: socfpga: stratix10: add L2 cache info
This removes cacheinfo warnings at boot, e.g.:
cacheinfo: Unable to detect cache hierarchy for CPU 0
Signed-off-by: Beniamin Sandu <beniaminsandu@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/altera')
| -rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index cbbc53c47921..0def0b0daaf7 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -34,6 +34,7 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x0>; }; @@ -41,6 +42,7 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x1>; }; @@ -48,6 +50,7 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x2>; }; @@ -55,8 +58,15 @@ compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&l2_shared>; reg = <0x3>; }; + + l2_shared: cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; }; firmware { |