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| author | Icenowy Zheng <icenowy@aosc.io> | 2018-05-04 02:38:44 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-05-04 17:08:18 +0200 |
| commit | 71f9bdbd4d291b3883fbda7ebeb6efae68e55f32 (patch) | |
| tree | 94fa5e841f7cd7724e822e9dd5c207398d3c5a4b /arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | |
| parent | 05bdee31e0eefa4abeb183fc2400f57cf5f74688 (diff) | |
| download | lwn-71f9bdbd4d291b3883fbda7ebeb6efae68e55f32.tar.gz lwn-71f9bdbd4d291b3883fbda7ebeb6efae68e55f32.zip | |
arm64: allwinner: h6: add node for R_PIO pin controller
Allwinner H6 SoC has a R_PIO pin controller which controls PL and PM
GPIO banks.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index db9da343ba46..a1d19f923fdf 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -183,5 +183,18 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun50i-h6-r-pinctrl"; + reg = <0x07022000 0x400>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu 2>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + }; }; }; |