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| author | Ben Dooks <ben-linux@fluff.org> | 2008-12-12 00:24:30 +0000 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2009-05-07 11:04:56 +0100 |
| commit | d87964c46005ccb04754f6309df0fd8f67b08c6d (patch) | |
| tree | d35fc1fb3660dca0cdb236ef14ba27dcd69618f2 /arch/arm/plat-s3c24xx/gpiolib.c | |
| parent | 966bcc14386000e8b4dc7bbb426910bcb55a8588 (diff) | |
| download | lwn-d87964c46005ccb04754f6309df0fd8f67b08c6d.tar.gz lwn-d87964c46005ccb04754f6309df0fd8f67b08c6d.zip | |
[ARM] S3C: GPIO PM core GPIOlib integration
Move the GPIO suspend/resume support inline with the gpiolib support
so that it will work with both the S3C24XX and S3C64XX series.
The s3c_gpio_chip is extended to have a pm callback and a save block
to keep the state of the GPIO over suspend, and the code from the
s3c24xx implementation is added to a new common file.
The suspend process now uses the list of registered chips to go through
saving and restoring each one as appropriate, using the pm callback to
select the appropriate routine depending on the type of control register
present.
This change also means that any additional GPIO added should not require
changes to the PM.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/plat-s3c24xx/gpiolib.c')
| -rw-r--r-- | arch/arm/plat-s3c24xx/gpiolib.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c index 5c0491bf738b..4bac12dc0733 100644 --- a/arch/arm/plat-s3c24xx/gpiolib.c +++ b/arch/arm/plat-s3c24xx/gpiolib.c @@ -22,6 +22,7 @@ #include <mach/gpio-core.h> #include <mach/hardware.h> #include <asm/irq.h> +#include <plat/pm.h> #include <mach/regs-gpio.h> @@ -78,6 +79,7 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset) struct s3c_gpio_chip s3c24xx_gpios[] = { [0] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), + .pm = __gpio_pm(&s3c_gpio_pm_1bit), .chip = { .base = S3C2410_GPA0, .owner = THIS_MODULE, @@ -89,6 +91,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [1] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPB0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPB0, .owner = THIS_MODULE, @@ -98,6 +101,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [2] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPC0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPC0, .owner = THIS_MODULE, @@ -107,6 +111,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [3] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPD0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPD0, .owner = THIS_MODULE, @@ -116,6 +121,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [4] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPE0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPE0, .label = "GPIOE", @@ -125,6 +131,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [5] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPF0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPF0, .owner = THIS_MODULE, @@ -135,6 +142,7 @@ struct s3c_gpio_chip s3c24xx_gpios[] = { }, [6] = { .base = S3C24XX_GPIO_BASE(S3C2410_GPG0), + .pm = __gpio_pm(&s3c_gpio_pm_2bit), .chip = { .base = S3C2410_GPG0, .owner = THIS_MODULE, |