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| author | Philip Rakity <prakity@marvell.com> | 2010-11-19 16:48:39 -0500 |
|---|---|---|
| committer | Chris Ball <cjb@laptop.org> | 2010-11-22 15:12:04 -0500 |
| commit | 15ec44611904be0dcc97b84c29fbf964e5e2b36f (patch) | |
| tree | d64384c6bf47beee40172419a29b09c2943e964e /arch/arm/plat-pxa | |
| parent | ed919b0125b26dcc052e44836f66e7e1f5c49c7e (diff) | |
| download | lwn-15ec44611904be0dcc97b84c29fbf964e5e2b36f.tar.gz lwn-15ec44611904be0dcc97b84c29fbf964e5e2b36f.zip | |
mmc: sdhci: 8-bit bus width changes
We now:
* check for a v3 controller before setting 8-bit bus width
* offer a callback for platform code to switch to 8-bit mode, which
allows non-v3 controllers to support it
* rely on mmc->caps |= MMC_CAP_8_BIT_DATA; in platform code to specify
that the board designers have indeed brought out all the pins for
8-bit to the slot.
We were previously relying only on whether the *controller* supported
8-bit, which doesn't tell us anything about the pin configuration in
the board design.
This fixes the MMC card regression reported by Maxim Levitsky here:
http://thread.gmane.org/gmane.linux.kernel.mmc/4336
by no longer assuming that 8-bit works by default.
Signed-off-by: Philip Rakity <prakity@marvell.com>
Tested-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'arch/arm/plat-pxa')
| -rw-r--r-- | arch/arm/plat-pxa/include/plat/sdhci.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/plat-pxa/include/plat/sdhci.h b/arch/arm/plat-pxa/include/plat/sdhci.h index e49c5b6fc4e2..1ab332e37d7d 100644 --- a/arch/arm/plat-pxa/include/plat/sdhci.h +++ b/arch/arm/plat-pxa/include/plat/sdhci.h @@ -17,6 +17,9 @@ /* Require clock free running */ #define PXA_FLAG_DISABLE_CLOCK_GATING (1<<0) +/* Board design supports 8-bit data on SD/SDIO BUS */ +#define PXA_FLAG_SD_8_BIT_CAPABLE_SLOT (1<<2) + /* * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI * @max_speed: the maximum speed supported |