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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2005-09-30 08:39:56 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-09-30 08:39:56 -0700 |
| commit | 1dd465cac8d3ba18a9840d032f6604147269c031 (patch) | |
| tree | 78f00fdeae26d018def75e7517aa50e56f4994df /arch/arm/mm | |
| parent | a2218cac0aacecbecebd3cabc43cc8a4a09cecbb (diff) | |
| parent | 217874feed0d3a6543a6b7127782f4a08bffd731 (diff) | |
| download | lwn-1dd465cac8d3ba18a9840d032f6604147269c031.tar.gz lwn-1dd465cac8d3ba18a9840d032f6604147269c031.zip | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/cache-v6.S | 9 | ||||
| -rw-r--r-- | arch/arm/mm/flush.c | 36 |
2 files changed, 26 insertions, 19 deletions
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 85c10a71e7c6..72966d90e956 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -18,6 +18,7 @@ #define HARVARD_CACHE #define CACHE_LINE_SIZE 32 #define D_CACHE_LINE_SIZE 32 +#define BTB_FLUSH_SIZE 8 /* * v6_flush_cache_all() @@ -98,7 +99,13 @@ ENTRY(v6_coherent_user_range) mcr p15, 0, r0, c7, c5, 1 @ invalidate I line #endif mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #CACHE_LINE_SIZE + add r0, r0, #BTB_FLUSH_SIZE + mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry + add r0, r0, #BTB_FLUSH_SIZE + mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry + add r0, r0, #BTB_FLUSH_SIZE + mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry + add r0, r0, #BTB_FLUSH_SIZE cmp r0, r1 blo 1b #ifdef HARVARD_CACHE diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index b0208c992576..c9a03981b785 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -17,6 +17,24 @@ #ifdef CONFIG_CPU_CACHE_VIPT +#define ALIAS_FLUSH_START 0xffff4000 + +#define TOP_PTE(x) pte_offset_kernel(top_pmd, x) + +static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) +{ + unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); + + set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL)); + flush_tlb_kernel_page(to); + + asm( "mcrr p15, 0, %1, %0, c14\n" + " mcrr p15, 0, %1, %0, c5\n" + : + : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES) + : "cc"); +} + void flush_cache_mm(struct mm_struct *mm) { if (cache_is_vivt()) { @@ -67,24 +85,6 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig if (cache_is_vipt_aliasing()) flush_pfn_alias(pfn, user_addr); } - -#define ALIAS_FLUSH_START 0xffff4000 - -#define TOP_PTE(x) pte_offset_kernel(top_pmd, x) - -static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) -{ - unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); - - set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL)); - flush_tlb_kernel_page(to); - - asm( "mcrr p15, 0, %1, %0, c14\n" - " mcrr p15, 0, %1, %0, c5\n" - : - : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES) - : "cc"); -} #else #define flush_pfn_alias(pfn,vaddr) do { } while (0) #endif |