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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-04-07 13:17:15 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-04-07 13:23:57 +0100 |
| commit | 95f3df6bcb89d370c57b7165f55c5a409d011c8e (patch) | |
| tree | 9accc55603a6274a281fce6950fbef26f051a2c5 /arch/arm/mm/proc-sa110.S | |
| parent | f1dc24d53e9e91cf795f05751eeb7e220c7c15e1 (diff) | |
| download | lwn-95f3df6bcb89d370c57b7165f55c5a409d011c8e.tar.gz lwn-95f3df6bcb89d370c57b7165f55c5a409d011c8e.zip | |
[ARM] Fix SA110/SA1100 cache flushing
We had two implementations for flushing the cache, which meant StrongARM
caches weren't being correctly flushed. Fix this by always using the
v4wb_flush_kern_cache_all method, rather than duplicating it.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-sa110.S')
| -rw-r--r-- | arch/arm/mm/proc-sa110.S | 25 |
1 files changed, 4 insertions, 21 deletions
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index c916a6cae404..a2dd5ae1077d 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S @@ -26,22 +26,7 @@ * the cache line size of the I and D cache */ #define DCACHELINESIZE 32 -#define FLUSH_OFFSET 32768 - .macro flush_110_dcache rd, ra, re - ldr \rd, =flush_base - ldr \ra, [\rd] - eor \ra, \ra, #FLUSH_OFFSET - str \ra, [\rd] - add \re, \ra, #16384 @ only necessary for 16k -1001: ldr \rd, [\ra], #DCACHELINESIZE - teq \re, \ra - bne 1001b - .endm - - .data -flush_base: - .long FLUSH_BASE .text /* @@ -145,13 +130,11 @@ ENTRY(cpu_sa110_dcache_clean_area) */ .align 5 ENTRY(cpu_sa110_switch_mm) - flush_110_dcache r3, ip, r1 - mov r1, #0 - mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache - mcr p15, 0, r1, c7, c10, 4 @ drain WB + str lr, [sp, #-4]! + bl v4wb_flush_kern_cache_all @ clears IP mcr p15, 0, r0, c2, c0, 0 @ load page table pointer - mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs - mov pc, lr + mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs + ldr pc, [sp], #4 /* * cpu_sa110_set_pte(ptep, pte) |