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| author | Ben Dooks <ben-linux@fluff.org> | 2008-01-28 13:01:34 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-01-28 13:20:52 +0000 |
| commit | 3a38e4be76e86c7b94c36dc8f3ce489987da24e4 (patch) | |
| tree | 1b8ce87d0002c28fe9a8615151a28a3b666f5c17 /arch/arm/mach-s3c2442 | |
| parent | c27cb681ac1598352569f75cb19850a12b7ef102 (diff) | |
| download | lwn-3a38e4be76e86c7b94c36dc8f3ce489987da24e4.tar.gz lwn-3a38e4be76e86c7b94c36dc8f3ce489987da24e4.zip | |
[ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code
Merge together the bits of the S3C2440 and S3C2442 clock code
that can be.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-s3c2442')
| -rw-r--r-- | arch/arm/mach-s3c2442/clock.c | 22 |
1 files changed, 1 insertions, 21 deletions
diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c index 5b9e830ac4d3..2d030d439fe9 100644 --- a/arch/arm/mach-s3c2442/clock.c +++ b/arch/arm/mach-s3c2442/clock.c @@ -115,14 +115,9 @@ static struct clk s3c2442_clk_cam_upll = { static int s3c2442_clk_add(struct sys_device *sysdev) { - unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); - unsigned long clkdivn; + struct clk *clock_upll; struct clk *clock_h; struct clk *clock_p; - struct clk *clock_upll; - - printk("S3C2442: Clock Support, DVS %s\n", - (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off"); clock_p = clk_get(NULL, "pclk"); clock_h = clk_get(NULL, "hclk"); @@ -133,21 +128,6 @@ static int s3c2442_clk_add(struct sys_device *sysdev) return -EINVAL; } - /* check rate of UPLL, and if it is near 96MHz, then change - * to using half the UPLL rate for the system */ - - if (clk_get_rate(clock_upll) > (94 * MHZ)) { - clk_usb_bus.rate = clk_get_rate(clock_upll) / 2; - - mutex_lock(&clocks_mutex); - - clkdivn = __raw_readl(S3C2410_CLKDIVN); - clkdivn |= S3C2440_CLKDIVN_UCLK; - __raw_writel(clkdivn, S3C2410_CLKDIVN); - - mutex_unlock(&clocks_mutex); - } - s3c2442_clk_cam.parent = clock_h; s3c2442_clk_cam_upll.parent = clock_upll; |