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author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-10-13 11:06:57 -0700 |
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committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-10-13 11:07:13 -0700 |
commit | 1a5a2cbd21e58a824688ae2120a3e47b3cd0f876 (patch) | |
tree | 1ed6bc7f0953bc81f2f7b48639bd6239c93b9dad /arch/arm/mach-s3c/mach-mini2440.c | |
parent | 6224db7881936c8e1c3b352b5debbbbd8856911a (diff) | |
parent | da29dbcda49d60f34055df19bd4783b889fc7dfc (diff) | |
download | lwn-1a5a2cbd21e58a824688ae2120a3e47b3cd0f876.tar.gz lwn-1a5a2cbd21e58a824688ae2120a3e47b3cd0f876.zip |
Merge patch series "Use composable cache instead of L2 cache"
Zong Li <zong.li@sifive.com> says:
Since composable cache may be L3 cache if private L2 cache exists, we
should use its original name "composable cache" to prevent confusion.
This patchset contains the modification which is related to ccache, such
as DT binding and EDAC driver.
* b4-shazam-merge:
riscv: Add cache information in AUX vector
soc: sifive: ccache: define the macro for the register shifts
soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes
soc: sifive: ccache: reduce printing on init
soc: sifive: ccache: determine the cache level from dts
soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.
dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache
Link: https://lore.kernel.org/r/20220913061817.22564-1-zong.li@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/arm/mach-s3c/mach-mini2440.c')
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