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authorTzachi Perelstein <tzachi@marvell.com>2007-10-23 15:14:41 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-01-26 15:03:42 +0000
commit585cf17561d3174a745bec49c422c1a621c95fc4 (patch)
tree66f0ff02c844a4bf22dcbca66b2babf387b4f628 /arch/arm/mach-orion/common.c
parentd910a0aa21c9c6e824744d0139bbe6a9ae676e2d (diff)
downloadlwn-585cf17561d3174a745bec49c422c1a621c95fc4.tar.gz
lwn-585cf17561d3174a745bec49c422c1a621c95fc4.zip
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces, and, depending on the specific model, PCI-E interface, PCI-X interface, SATA controllers, crypto unit, SPI interface, SDIO interface, device bus, NAND controller, DMA engine and/or XOR engine. This contains the basic structure and architecture register definitions. Signed-off-by: Tzachi Perelstein <tzachi@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Reviewed-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-orion/common.c')
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diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion/common.c
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+/*
+ * arch/arm/mach-orion/common.c
+ *
+ * Core functions for Marvell Orion System On Chip
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/arch/orion.h>
+#include "common.h"
+
+/*****************************************************************************
+ * I/O Address Mapping
+ ****************************************************************************/
+static struct map_desc orion_io_desc[] __initdata = {
+ {
+ .virtual = ORION_REGS_BASE,
+ .pfn = __phys_to_pfn(ORION_REGS_BASE),
+ .length = ORION_REGS_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = ORION_PCIE_IO_BASE,
+ .pfn = __phys_to_pfn(ORION_PCIE_IO_BASE),
+ .length = ORION_PCIE_IO_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = ORION_PCI_IO_BASE,
+ .pfn = __phys_to_pfn(ORION_PCI_IO_BASE),
+ .length = ORION_PCI_IO_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = ORION_PCIE_WA_BASE,
+ .pfn = __phys_to_pfn(ORION_PCIE_WA_BASE),
+ .length = ORION_PCIE_WA_SIZE,
+ .type = MT_DEVICE
+ },
+};
+
+void __init orion_map_io(void)
+{
+ iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc));
+}