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| author | Nishanth Menon <nm@ti.com> | 2014-06-12 17:15:22 +0530 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-07-21 23:32:51 -0700 |
| commit | 76be4a54157ab0059fb29d8d516db46d239812e2 (patch) | |
| tree | 434db5329e5a6facbc1ca84bfac6c20daf9c7972 /arch/arm/mach-omap2 | |
| parent | 3db53918e306d3960bf9e12eea8b2fd3f7d0fd62 (diff) | |
| download | lwn-76be4a54157ab0059fb29d8d516db46d239812e2.tar.gz lwn-76be4a54157ab0059fb29d8d516db46d239812e2.zip | |
ARM: OMAP2+: DMA: remove requirement of irq for platform-dma driver
we have currently 2 DMA drivers that try to co-exist.
drivers/dma/omap-dma.c which registers it's own IRQ and is device tree
aware and uses arch/arm/plat-omap/dma.c instance created by
arch/arm/mach-omap2/dma.c to maintain channel usage (omap_request_dma).
Currently both try to register interrupts and mach-omap2/plat-omap dma.c
attempts to use the IRQ number registered by hwmod to register it's own
interrupt handler.
Now, there is no reasonable way of static allocating DMA irq in GIC
SPI when we use crossbar. However, since the dma_chan structure is
freed as a result of IRQ not being present due to devm allocation,
maintaining information of channel by platform code fails at a later
point in time when that region of memory is reused.
So, if hwmod does not indicate an IRQ number, then, assume that
dma-engine will take care of the interrupt handling.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/dma.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index a6d2cf1f8d02..e1a56d87599e 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -259,6 +259,9 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) d->dev_caps |= HS_CHANNELS_RESERVED; + if (platform_get_irq_byname(pdev, "0") < 0) + d->dev_caps |= DMA_ENGINE_HANDLE_IRQ; + /* Check the capabilities register for descriptor loading feature */ if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) dma_common_ch_end = CCDN; |