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author | Tony Lindgren <tony@atomide.com> | 2021-03-10 14:03:53 +0200 |
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committer | Tony Lindgren <tony@atomide.com> | 2021-03-10 14:04:07 +0200 |
commit | ca319f4f41a3bf76f1875fcc5003ba1a99443f8b (patch) | |
tree | e0a61bb2de7b38226af2538f4a239dbca6286183 /arch/arm/mach-omap2 | |
parent | 47a4b458c18484f9e3fb6c358054dae3984940e0 (diff) | |
download | lwn-ca319f4f41a3bf76f1875fcc5003ba1a99443f8b.tar.gz lwn-ca319f4f41a3bf76f1875fcc5003ba1a99443f8b.zip |
ARM: OMAP2+: Drop legacy platform data for dra7 l4_per2
We can now probe interconnects with simple-pm-bus and genpd.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 75 |
1 files changed, 1 insertions, 74 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index cb3171ae1280..77553a81d32b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -81,7 +81,7 @@ static struct omap_hwmod dra7xx_l3_main_2_hwmod = { /* * 'l4' class - * instance(s): l4_cfg, l4_per2, l4_per3 + * instance(s): l4_cfg, l4_per3 */ static struct omap_hwmod_class dra7xx_l4_hwmod_class = { .name = "l4", @@ -100,19 +100,6 @@ static struct omap_hwmod dra7xx_l4_cfg_hwmod = { }, }; -/* l4_per2 */ -static struct omap_hwmod dra7xx_l4_per2_hwmod = { - .name = "l4_per2", - .class = &dra7xx_l4_hwmod_class, - .clkdm_name = "l4per2_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET, - .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, - }, - }, -}; - /* l4_per3 */ static struct omap_hwmod dra7xx_l4_per3_hwmod = { .name = "l4_per3", @@ -127,30 +114,6 @@ static struct omap_hwmod dra7xx_l4_per3_hwmod = { }; /* - * 'atl' class - * - */ - -static struct omap_hwmod_class dra7xx_atl_hwmod_class = { - .name = "atl", -}; - -/* atl */ -static struct omap_hwmod dra7xx_atl_hwmod = { - .name = "atl", - .class = &dra7xx_atl_hwmod_class, - .clkdm_name = "atl_clkdm", - .main_clk = "atl_gfclk_mux", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* * 'bb2d' class * */ @@ -257,14 +220,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_main_1 -> l4_per2 */ -static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = { - .master = &dra7xx_l3_main_1_hwmod, - .slave = &dra7xx_l4_per2_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> l4_per3 */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = { .master = &dra7xx_l3_main_1_hwmod, @@ -273,14 +228,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_per2 -> atl */ -static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = { - .master = &dra7xx_l4_per2_hwmod, - .slave = &dra7xx_atl_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> bb2d */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = { .master = &dra7xx_l3_main_1_hwmod, @@ -297,14 +244,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_per2 -> vcp1 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = { - .master = &dra7xx_l4_per2_hwmod, - .slave = &dra7xx_vcp1_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> vcp2 */ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = { .master = &dra7xx_l3_main_1_hwmod, @@ -313,28 +252,16 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_per2 -> vcp2 */ -static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = { - .master = &dra7xx_l4_per2_hwmod, - .slave = &dra7xx_vcp2_hwmod, - .clk = "l3_iclk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_2__l3_instr, &dra7xx_l4_cfg__l3_main_1, &dra7xx_l3_main_1__l3_main_2, &dra7xx_l4_cfg__l3_main_2, &dra7xx_l3_main_1__l4_cfg, - &dra7xx_l3_main_1__l4_per2, &dra7xx_l3_main_1__l4_per3, - &dra7xx_l4_per2__atl, &dra7xx_l3_main_1__bb2d, &dra7xx_l3_main_1__vcp1, - &dra7xx_l4_per2__vcp1, &dra7xx_l3_main_1__vcp2, - &dra7xx_l4_per2__vcp2, NULL, }; |