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| author | Lennert Buytenhek <buytenh@wantstofly.org> | 2008-10-20 01:51:04 +0200 |
|---|---|---|
| committer | Nicolas Pitre <nico@cam.org> | 2008-12-20 12:27:13 -0500 |
| commit | b95a13d79c0e92c9c844fa8aa089c9bd2ed10705 (patch) | |
| tree | e1c4c855de14abe955d12e6436eb8dca64dad027 /arch/arm/mach-mv78xx0/irq.c | |
| parent | 4c21343005b6b0d6ef24ab6e6a8f3883ff0cb569 (diff) | |
| download | lwn-b95a13d79c0e92c9c844fa8aa089c9bd2ed10705.tar.gz lwn-b95a13d79c0e92c9c844fa8aa089c9bd2ed10705.zip | |
[ARM] mv78xx0: implement GPIO and GPIO interrupt support
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mach-mv78xx0/irq.c')
| -rw-r--r-- | arch/arm/mach-mv78xx0/irq.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 503e5d195ae5..e273418797b4 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -11,13 +11,42 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/pci.h> +#include <linux/irq.h> +#include <asm/gpio.h> #include <mach/mv78xx0.h> #include <plat/irq.h> #include "common.h" +static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31); + + orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3); +} + void __init mv78xx0_init_irq(void) { + int i; + orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); + + /* + * Mask and clear GPIO IRQ interrupts. + */ + writel(0, GPIO_LEVEL_MASK(0)); + writel(0, GPIO_EDGE_MASK(0)); + writel(0, GPIO_EDGE_CAUSE(0)); + + for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) { + set_irq_chip(i, &orion_gpio_irq_level_chip); + set_irq_handler(i, handle_level_irq); + irq_desc[i].status |= IRQ_LEVEL; + set_irq_flags(i, IRQF_VALID); + } + set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); + set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); + set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); + set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); } |