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| author | Richard Cochran <richardcochran@gmail.com> | 2011-07-15 21:33:12 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-07-15 18:02:35 -0700 |
| commit | 900b170af40b4fef54e89f3d48d055f7d8031ae6 (patch) | |
| tree | 3a7a4fba6d5efd200eeab0eabbaf1d6fd632c894 /arch/arm/mach-ixp4xx | |
| parent | af8a927c8bdea82cf220e0b720d64daaf073a969 (diff) | |
| download | lwn-900b170af40b4fef54e89f3d48d055f7d8031ae6.tar.gz lwn-900b170af40b4fef54e89f3d48d055f7d8031ae6.zip | |
ARM: fix regression in IXP4xx clocksource
Commit 234b6ceddb4fc2a4bc5b9a7670f070f6e69e0868
clocksource: convert ARM 32-bit up counting clocksources
broke the build for ixp4xx and made big endian operation impossible.
This commit restores the original behaviour.
Signed-off-by: Richard Cochran <richard.cochran@omicron.at>
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
[ Thomas says that we might want to have generic BE accessor functions
to the MMIO clock source, but that hasn't happened yet, so in the
meantime this seems to be the short-term fix for the particular
problem - Linus ]
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/arm/mach-ixp4xx')
| -rw-r--r-- | arch/arm/mach-ixp4xx/common.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 74ed81a3cb1a..07772575d7ab 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -419,14 +419,20 @@ static void notrace ixp4xx_update_sched_clock(void) /* * clocksource */ + +static cycle_t ixp4xx_clocksource_read(struct clocksource *c) +{ + return *IXP4XX_OSTS; +} + unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ; EXPORT_SYMBOL(ixp4xx_timer_freq); static void __init ixp4xx_clocksource_init(void) { init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq); - clocksource_mmio_init(&IXP4XX_OSTS, "OSTS", ixp4xx_timer_freq, 200, 32, - clocksource_mmio_readl_up); + clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32, + ixp4xx_clocksource_read); } /* |