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author | Fabio Estevam <fabio.estevam@nxp.com> | 2018-07-10 13:31:48 -0300 |
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committer | Shawn Guo <shawnguo@kernel.org> | 2018-07-12 09:52:20 +0800 |
commit | 26b754f99402d6e7fc4e07d67a2597e6ebabde8b (patch) | |
tree | 952de042c8ac68e8ce02a210c63e062777db151a /arch/arm/mach-imx/cpu-imx5.c | |
parent | 11d973de60e1a69e2b0b240557ad02cf9f884d71 (diff) | |
download | lwn-26b754f99402d6e7fc4e07d67a2597e6ebabde8b.tar.gz lwn-26b754f99402d6e7fc4e07d67a2597e6ebabde8b.zip |
ARM: mx5: Set the DBGEN bit in ARM_GPC register
On i.MX51/i.MX53 it is necessary to set the DBGEN bit in
ARM_GPC register in order to turn on the debug clocks.
The DBGEN bit of ARM_GPC register has the following description
in the i.MX53 Reference Manual:
"This allows the user to manually activate clocks within the debug
system. This register bit directly controls the platform's dbgen_out
output signal which connects to the DAP_SYS to enable all debug clocks.
Once enabled, the clocks cannot be disabled except by asserting the
disable_trace input of the DAP_SYS."
Based on a previous patch from Sebastian Reichel.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/mach-imx/cpu-imx5.c')
-rw-r--r-- | arch/arm/mach-imx/cpu-imx5.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/cpu-imx5.c b/arch/arm/mach-imx/cpu-imx5.c index 4f2d1c772f85..e210bac18840 100644 --- a/arch/arm/mach-imx/cpu-imx5.c +++ b/arch/arm/mach-imx/cpu-imx5.c @@ -117,3 +117,48 @@ int mx53_revision(void) return mx5_cpu_rev; } EXPORT_SYMBOL(mx53_revision); + +#define ARM_GPC 0x4 +#define DBGEN BIT(16) + +/* + * This enables the DBGEN bit in ARM_GPC register, which is + * required for accessing some performance counter features. + * Technically it is only required while perf is used, but to + * keep the source code simple we just enable it all the time + * when the kernel configuration allows using the feature. + */ +void __init imx5_pmu_init(void) +{ + void __iomem *tigerp_base; + struct device_node *np; + u32 gpc; + + if (!IS_ENABLED(CONFIG_ARM_PMU)) + return; + + np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); + if (!np) + return; + + if (!of_property_read_bool(np, "secure-reg-access")) + goto exit; + + of_node_put(np); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx51-tigerp"); + if (!np) + return; + + tigerp_base = of_iomap(np, 0); + if (!tigerp_base) + goto exit; + + gpc = readl_relaxed(tigerp_base + ARM_GPC); + gpc |= DBGEN; + writel_relaxed(gpc, tigerp_base + ARM_GPC); + iounmap(tigerp_base); +exit: + of_node_put(np); + +} |