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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2011-11-18 01:41:28 +0800 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2012-01-20 17:22:50 +0100 |
| commit | 14f991a730f453a1c8f114ccb686f83e158fdd92 (patch) | |
| tree | cebc0df6224f92f7e554b96bad2daf7e4fe13a64 /arch/arm/mach-at91/Kconfig | |
| parent | e9f68b5cc6160a473fc668054fd13f435fd4508b (diff) | |
| download | lwn-14f991a730f453a1c8f114ccb686f83e158fdd92.tar.gz lwn-14f991a730f453a1c8f114ccb686f83e158fdd92.zip | |
ARM: at91: Fix at91sam9g45 and at91cap9 reset
As on the other sam9 we need to cleanly shutdown the DDRAM before rebooting.
On those SoC the SDRAM/DDRAM controller is different. So, the assembly code
ends up being not cleanly combined with previous at91sam9_alt_restart function.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/Kconfig')
| -rw-r--r-- | arch/arm/mach-at91/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 4275577fddc2..71feb00a1e99 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -21,6 +21,9 @@ config HAVE_AT91_USART5 config AT91_SAM9_ALT_RESET bool +config AT91_SAM9G45_RESET + bool + menu "Atmel AT91 System-on-Chip" choice @@ -97,6 +100,7 @@ config ARCH_AT91SAM9G45 select HAVE_FB_ATMEL select HAVE_NET_MACB select HAVE_AT91_DBGU1 + select AT91_SAM9G45_RESET config ARCH_AT91CAP9 bool "AT91CAP9" @@ -105,6 +109,7 @@ config ARCH_AT91CAP9 select HAVE_FB_ATMEL select HAVE_NET_MACB select HAVE_AT91_DBGU1 + select AT91_SAM9G45_RESET config ARCH_AT91X40 bool "AT91x40" |