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| author | Andre Przywara <andre.przywara@arm.com> | 2020-09-07 13:18:27 +0100 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2020-10-03 12:56:56 -0700 |
| commit | e916bfacf558ee835c480d2c2dad9d144baf9e1c (patch) | |
| tree | eafaa96b7776cc0aca510424c0081ef29d65b454 /arch/arm/boot | |
| parent | c9794866ac30d9440b327e96b4ecc97d8f0055f6 (diff) | |
| download | lwn-e916bfacf558ee835c480d2c2dad9d144baf9e1c.tar.gz lwn-e916bfacf558ee835c480d2c2dad9d144baf9e1c.zip | |
ARM: dts: nspire: Fix SP804 users
Even though the SP804 binding allows to specify only one clock, the
primecell driver requires a named clock to activate the bus clock.
Specify the one clock three times and provide some clock-names, to
make the DT match the SP804 and primecell binding.
Link: https://lore.kernel.org/r/20200907121831.242281-3-andre.przywara@arm.com
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/nspire.dtsi | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index d9a0fd7524dc..90e033d9141f 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -145,15 +145,19 @@ timer0: timer@900C0000 { reg = <0x900C0000 0x1000>; - - clocks = <&timer_clk>; + clocks = <&timer_clk>, <&timer_clk>, + <&timer_clk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; }; timer1: timer@900D0000 { reg = <0x900D0000 0x1000>; interrupts = <19>; - - clocks = <&timer_clk>; + clocks = <&timer_clk>, <&timer_clk>, + <&timer_clk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; }; watchdog: watchdog@90060000 { |