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authorPawel Moll <pawel.moll@arm.com>2012-05-10 17:12:07 +0100
committerPawel Moll <pawel.moll@arm.com>2012-05-21 09:30:37 +0100
commite29b65dbc5d0431e8f063fab19fafaaa744d55ce (patch)
treea0e08c67f6b7f1d47fdf30cf3a95f730b825a6b7 /arch/arm/boot/dts/vexpress-v2p-ca5s.dts
parent76e10d158efb6d4516018846f60c2ab5501900bc (diff)
downloadlwn-e29b65dbc5d0431e8f063fab19fafaaa744d55ce.tar.gz
lwn-e29b65dbc5d0431e8f063fab19fafaaa744d55ce.zip
ARM: vexpress: Device Tree updates
* Added extra regs for A15 VGIC * Added A15 architected timer node * Split A5 and A9 TWD nodes into two separate ones for timer and watchdog; interrupt definitions fixed on the way * Fixed typo in A5 GIC compatible value All the changes courtesy of Marc Zyngier. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Diffstat (limited to 'arch/arm/boot/dts/vexpress-v2p-ca5s.dts')
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts13
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 6905e66d4748..18917a0f8604 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -77,13 +77,18 @@
timer@2c000600 {
compatible = "arm,cortex-a5-twd-timer";
- reg = <0x2c000600 0x38>;
- interrupts = <1 2 0x304>,
- <1 3 0x304>;
+ reg = <0x2c000600 0x20>;
+ interrupts = <1 13 0x304>;
+ };
+
+ watchdog@2c000620 {
+ compatible = "arm,cortex-a5-twd-wdt";
+ reg = <0x2c000620 0x20>;
+ interrupts = <1 14 0x304>;
};
gic: interrupt-controller@2c001000 {
- compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic";
+ compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;