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authorPawel Moll <pawel.moll@arm.com>2012-09-17 16:43:30 +0100
committerPawel Moll <pawel.moll@arm.com>2012-11-05 17:09:50 +0000
commit842839a37a9a9ac12d88930b6605c620fc09bc1d (patch)
tree58cb6e8d1b4f7eab6edb8425eed039dd8e966c92 /arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
parent88e0abcd7a8171ca7af3402373e7bd81fe9b6754 (diff)
downloadlwn-842839a37a9a9ac12d88930b6605c620fc09bc1d.tar.gz
lwn-842839a37a9a9ac12d88930b6605c620fc09bc1d.zip
ARM: vexpress: Add config bus components and clocks to DTs
Add description of all functions provided by Versatile Express motherboard and daughterboards configuration controllers and clock dependencies between devices. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Diffstat (limited to 'arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts')
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts110
1 files changed, 110 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index d12b34ca0568..4bbed10de45b 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -12,6 +12,7 @@
/ {
model = "V2P-CA15";
arm,hbi = <0x237>;
+ arm,vexpress,site = <0xf>;
compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
@@ -54,17 +55,24 @@
compatible = "arm,hdlcd";
reg = <0 0x2b000000 0 0x1000>;
interrupts = <0 85 4>;
+ clocks = <&oscclk5>;
+ clock-names = "pxlclk";
};
memory-controller@2b0a0000 {
compatible = "arm,pl341", "arm,primecell";
reg = <0 0x2b0a0000 0 0x1000>;
+ clocks = <&oscclk7>;
+ clock-names = "apb_pclk";
};
wdt@2b060000 {
compatible = "arm,sp805", "arm,primecell";
+ status = "disabled";
reg = <0 0x2b060000 0 0x1000>;
interrupts = <98>;
+ clocks = <&oscclk7>;
+ clock-names = "apb_pclk";
};
gic: interrupt-controller@2c001000 {
@@ -84,6 +92,8 @@
reg = <0 0x7ffd0000 0 0x1000>;
interrupts = <0 86 4>,
<0 87 4>;
+ clocks = <&oscclk7>;
+ clock-names = "apb_pclk";
};
dma@7ffb0000 {
@@ -94,6 +104,8 @@
<0 89 4>,
<0 90 4>,
<0 91 4>;
+ clocks = <&oscclk7>;
+ clock-names = "apb_pclk";
};
timer {
@@ -110,6 +122,104 @@
<0 69 4>;
};
+ dcc {
+ compatible = "arm,vexpress,config-bus";
+ arm,vexpress,config-bridge = <&v2m_sysreg>;
+
+ osc@0 {
+ /* CPU PLL reference clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 0>;
+ freq-range = <50000000 60000000>;
+ #clock-cells = <0>;
+ clock-output-names = "oscclk0";
+ };
+
+ osc@4 {
+ /* Multiplexed AXI master clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 4>;
+ freq-range = <20000000 40000000>;
+ #clock-cells = <0>;
+ clock-output-names = "oscclk4";
+ };
+
+ oscclk5: osc@5 {
+ /* HDLCD PLL reference clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 5>;
+ freq-range = <23750000 165000000>;
+ #clock-cells = <0>;
+ clock-output-names = "oscclk5";
+ };
+
+ smbclk: osc@6 {
+ /* SMB clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 6>;
+ freq-range = <20000000 50000000>;
+ #clock-cells = <0>;
+ clock-output-names = "oscclk6";
+ };
+
+ oscclk7: osc@7 {
+ /* SYS PLL reference clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 7>;
+ freq-range = <20000000 60000000>;
+ #clock-cells = <0>;
+ clock-output-names = "oscclk7";
+ };
+
+ osc@8 {
+ /* DDR2 PLL reference clock */
+ compatible = "arm,vexpress-osc";
+ arm,vexpress-sysreg,func = <1 8>;
+ freq-range = <40000000 40000000>;
+ #clock-cells = <0>;
+ clock-output-names = "oscclk8";
+ };
+
+ volt@0 {
+ /* CPU core voltage */
+ compatible = "arm,vexpress-volt";
+ arm,vexpress-sysreg,func = <2 0>;
+ regulator-name = "Cores";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ label = "Cores";
+ };
+
+ amp@0 {
+ /* Total current for the two cores */
+ compatible = "arm,vexpress-amp";
+ arm,vexpress-sysreg,func = <3 0>;
+ label = "Cores";
+ };
+
+ temp@0 {
+ /* DCC internal temperature */
+ compatible = "arm,vexpress-temp";
+ arm,vexpress-sysreg,func = <4 0>;
+ label = "DCC";
+ };
+
+ power@0 {
+ /* Total power */
+ compatible = "arm,vexpress-power";
+ arm,vexpress-sysreg,func = <12 0>;
+ label = "Cores";
+ };
+
+ energy@0 {
+ /* Total energy */
+ compatible = "arm,vexpress-energy";
+ arm,vexpress-sysreg,func = <13 0>;
+ label = "Cores";
+ };
+ };
+
motherboard {
ranges = <0 0 0 0x08000000 0x04000000>,
<1 0 0 0x14000000 0x04000000>,