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| author | Jay Agarwal <jagarwal@nvidia.com> | 2013-08-09 16:49:27 +0200 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-08-12 14:19:33 -0600 |
| commit | 89e7ada41674197387fa67ea0a853f3651b4e375 (patch) | |
| tree | 09b7de4ba3ff1070fb4f5ab10f8c2b14875eeeb1 /arch/arm/boot/dts/tegra30-cardhu.dtsi | |
| parent | e07e3dbd9c8f84ff37c117eb1ff80f3f41a4df4b (diff) | |
| download | lwn-89e7ada41674197387fa67ea0a853f3651b4e375.tar.gz lwn-89e7ada41674197387fa67ea0a853f3651b4e375.zip | |
ARM: tegra: Enable PCIe controller on Cardhu
Root port 2 is routed to the bottom connector on Cardhu and is used by
the development dock to provide gigabit ethernet and USB functionality.
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-cardhu.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra30-cardhu.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index d78c90cfaf1a..1ecd470e0c77 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -31,6 +31,26 @@ reg = <0x80000000 0x40000000>; }; + pcie-controller { + status = "okay"; + pex-clk-supply = <&pex_hvdd_3v3_reg>; + vdd-supply = <&ldo1_reg>; + avdd-supply = <&ldo2_reg>; + + pci@1,0 { + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; |