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| author | Dmitry Osipenko <digetx@gmail.com> | 2019-10-25 01:14:16 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-29 20:29:17 +0100 |
| commit | 4053aa65c517fba954af05e826bb97b2eaefe92a (patch) | |
| tree | 45d5b3ceff0104909792639f1e8fd68e17a3e5b6 /arch/arm/boot/dts/tegra30-cardhu-a04.dts | |
| parent | c01afebd74efe3e6de28f1a3c836afaccc2c97c9 (diff) | |
| download | lwn-4053aa65c517fba954af05e826bb97b2eaefe92a.tar.gz lwn-4053aa65c517fba954af05e826bb97b2eaefe92a.zip | |
ARM: tegra: cardhu-a04: Add CPU Operating Performance Points
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on
Cardhu A04.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-cardhu-a04.dts')
| -rw-r--r-- | arch/arm/boot/dts/tegra30-cardhu-a04.dts | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts index 0d71925d4f0b..9234988624ec 100644 --- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts +++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30-cardhu.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" /* This dts file support the cardhu A04 and later versions of board */ @@ -127,4 +129,26 @@ nvidia,tegra-core-regulator; }; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; }; |