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authorStephen Warren <swarren@nvidia.com>2011-10-11 16:16:13 -0600
committerOlof Johansson <olof@lixom.net>2011-10-11 17:19:56 -0700
commitf62f548c1c04742f68c15e21f173712dd6633791 (patch)
treeb5117bfb47d7d839aa19bc768b56525897a199e2 /arch/arm/boot/dts/tegra20.dtsi
parent940dd96fe9dec5b6ba4bb7ebc33212ff66db243c (diff)
downloadlwn-f62f548c1c04742f68c15e21f173712dd6633791.tar.gz
lwn-f62f548c1c04742f68c15e21f173712dd6633791.zip
arm/dt: Tegra: Add pinmux node to tegra20.dtsi
Add a pinmux node to tegra20.dtsi in order to instantiate the future pinmux device. v2: Specify reg property precisely; don't just point at the whole APB_MISC register range. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 5727595cde61..65d7e6a333eb 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -77,6 +77,14 @@
gpio-controller;
};
+ pinmux: pinmux@70000000 {
+ compatible = "nvidia,tegra20-pinmux";
+ reg = < 0x70000014 0x10 /* Tri-state registers */
+ 0x70000080 0x20 /* Mux registers */
+ 0x700000a0 0x14 /* Pull-up/down registers */
+ 0x70000868 0xa8 >; /* Pad control registers */
+ };
+
serial@70006000 {
compatible = "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;