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| author | Tuomas Tynkkynen <ttynkkynen@nvidia.com> | 2015-05-13 17:58:44 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-08-21 18:44:24 +0200 |
| commit | bf9d026775796bec30895cab080baf37b70bc3b3 (patch) | |
| tree | 0adf5b44a697ab661553f1ca2835f5591f9ad77c /arch/arm/boot/dts/tegra124-jetson-tk1.dts | |
| parent | 233da3b1c620b10a70c019b2134e7b1276b57695 (diff) | |
| download | lwn-bf9d026775796bec30895cab080baf37b70bc3b3.tar.gz lwn-bf9d026775796bec30895cab080baf37b70bc3b3.zip | |
ARM: tegra: Add the DFLL to Tegra124 device tree
The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124-jetson-tk1.dts')
0 files changed, 0 insertions, 0 deletions