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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-09-01 15:05:02 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-09-26 16:50:39 +0200 |
| commit | 94c3847dc5d18b56503415ef7733a4507061b1ca (patch) | |
| tree | 6d048eb6f5c14aea0b51bb72506ce2719a91ab93 /arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | |
| parent | 26e19cdf665f0998d30275877a7d5a14f908aa02 (diff) | |
| download | lwn-94c3847dc5d18b56503415ef7733a4507061b1ca.tar.gz lwn-94c3847dc5d18b56503415ef7733a4507061b1ca.zip | |
ARM: tegra: apalis-tk1: get rid of fake clocks simple bus
Get rid of the fake clocks simple bus and use node names as per the
actual schematics.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index 6d36521448ce..7fe61f1baadd 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -1931,17 +1931,10 @@ }; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - clk32k_in: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + clk32k_in: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; }; cpus { |