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| author | Andre Przywara <andre.przywara@arm.com> | 2020-01-02 01:26:56 +0000 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2020-01-03 10:39:27 +0100 |
| commit | 396c95e8b1385e3dac16d46227f570598b31f0f7 (patch) | |
| tree | e19159052df6bf0f1d8944462e4f27b77fe7d95b /arch/arm/boot/dts/sun8i-r40.dtsi | |
| parent | 7569ac447569b663ff1fc31484162e540fa000ab (diff) | |
| download | lwn-396c95e8b1385e3dac16d46227f570598b31f0f7.tar.gz lwn-396c95e8b1385e3dac16d46227f570598b31f0f7.zip | |
ARM: dts: sun8i: R40: Add PMU node
The ARM Cortex-A7 cores used in the Allwinner R40 SoC have their usual
Performance Monitoring Unit (PMU), which allows perf to use hardware
events.
The SoC integrator just needs to connect each per-core interrupt line
to the GIC. The R40 manual does not really mention those IRQ lines, but
experimentation in U-Boot shows that interrupts 152-155 are connected to
the four cores (similar to the A20).
Tested on a Bananapi M2 Berry, with perf and taskset to confirm the
association between cores and interrupts.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-r40.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-r40.dtsi | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 768dffb37117..8dcbc4465fbb 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -78,25 +78,25 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; @@ -884,6 +884,15 @@ }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |